`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/01/04 16:56:31
// Design Name: 
// Module Name: sm3_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module sm3_tb(

    );

//ʱ�Ӻ͸�λ
reg clk  ;
reg rst_n;

reg HWRITE,HSEL_1,HMASTLOOK;
reg [1:0] HTRANS;
reg [2:0] HSIZE,HBURST;
reg [3:0] HPROT;
reg [31:0] HWDATA,HADDR;
wire [31:0] HRDATA;
wire HRESP,HREADY;

integer ii,jj,kk;
integer sta_buf = 0;
//ʱ�����ڣ���λΪns�����ڴ��޸�ʱ�����ڡ�
parameter CYCLE    = 20, sm3_open = 32'hFFFF_FFDF, sm3_start = 32'hFFFF_FFCF, sm3_read = 32'hFFFF_FFD7,
    state_finish = 'd3;

always #(CYCLE/2) clk=!clk;

top_SM3 top_SM3_inst1(.HRESETn(rst_n),.HCLK(clk),.HWRITE(HWRITE),.HSEL(HSEL_1),.HMASTLOOK(HMASTLOOK),.HTRANS(HTRANS),.HSIZE(HSIZE),.HBURST(HBURST),.HPROT(HPROT),.HWDATA(HWDATA),.HADDR(HADDR),.HREADY(HREADY),.HRESP(HRESP),.HRDATA(HRDATA));
	//�����ź�din1��ֵ��ʽ
	initial begin
		clk = 1;
		rst_n = 0;
		HMASTLOOK = 1;
		HTRANS = 2'b0
		HSIZE = 3'b0;			
		HBURST= 3'b0;
		HPROT = 4'b0;
		#(10*CYCLE);
		rst_n = 1;
		#(CYCLE*2)
		@(posedge clk);
////////Reset SM3/////////////////	
		HSEL_1 = 1;
		HWRITE = 1;
		HADDR=32'h50002060;			
		HTRANS = 2'b10;
		HSIZE = 3'b010;			//32bit
		//#(CYCLE);	
		@(posedge clk);
		HSEL_1 = 0;
		HWRITE = 0;
		HADDR=32'h0;			
		HTRANS = 2'b0;
		HSIZE = 3'b0;			//32bit
		HWDATA= 32'hFFFF_FFFF;	//Reset SM3
	kk = 0;
    while(kk<4)begin
		jj = 0;
		while(jj<4)begin 
            #(CYCLE*4)
            @(posedge clk);		
            HSEL_1 = 1;
            HWRITE = 1;
            HADDR=32'h50002060;            
            HTRANS = 2'b10;
            HSIZE = 3'b010;            //32bit
//            #(CYCLE);
            @(posedge clk);  
            HSEL_1 = 0;
            HWRITE = 0;
            HADDR=32'h0;            
            HTRANS = 2'b0;
            HSIZE = 3'b0;            //32bit
            HWDATA= sm3_open; 
//////////////Message in////////////////  
            ii = 0;
            while(ii<16)
            begin
                #(CYCLE*4)
                @(posedge clk);
                HSEL_1 = 1;
                HWRITE = 1;
                HADDR  = 32'h50002000 + (ii*4);			
                HTRANS = 2'b10;
                HSIZE = 3'b010;			//32bit
                //#(CYCLE); 
                @(posedge clk);
                HSEL_1 = 0;
                HWRITE = 0;
                HADDR  = 32'h0;			
                HTRANS = 2'b0;
                HSIZE = 3'b0;			//32bit
                HWDATA= ii*(jj+1);	
                ii = ii+1;
            end
///////Start compute/////////////////
                    #(CYCLE*4)
//                     @(posedge clk);
                    HSEL_1 = 1;
                    HWRITE = 1;
                    HADDR=32'h50002060;            
                    HTRANS = 2'b10;
                    HSIZE = 3'b010;            //32bit
                    #(CYCLE);     
                    HSEL_1 = 0;
                    HWRITE = 0;
                    HADDR=32'h0;            
                    HTRANS = 2'b0;
                    HSIZE = 3'b0;            //32bit
                    HWDATA= sm3_start;
                    sta_buf = 0;
                    while(sta_buf != state_finish)begin
                        #(CYCLE*4)
 //                        @(posedge clk);
                        HSEL_1 = 1;
                        HWRITE = 0;        //Read status
                        HADDR=32'h50002064;            
                        HTRANS = 2'b10;
                        HSIZE = 3'b010;            //32bit
                        #(CYCLE);     
                        HSEL_1 = 0;
                        HWRITE = 0;
                        HADDR=32'h0;            
                        HTRANS = 2'b0;
                        HSIZE = 3'b0;            //32bit
			            #(CYCLE); 
                        sta_buf= HRDATA;        
                    end            
           jj = jj+1;		
		end
///////Read result/////////////////
		#(CYCLE*4)
//		 @(posedge clk);
		HSEL_1 = 1;
		HWRITE = 1;
		HADDR=32'h50002060;			
		HTRANS = 2'b10;
		HSIZE = 3'b010;			//32bit
		#(CYCLE); 
		HSEL_1 = 0;
		HWRITE = 0;
		HADDR=32'h0;			
		HTRANS = 2'b0;
		HSIZE = 3'b0;			//32bit
		HWDATA= sm3_read;
				
		ii = 0;
		while(ii<8)
		begin
			#(CYCLE*4)
//			 @(posedge clk);
			HSEL_1 = 1;
			HWRITE = 0;		//Read register
			HADDR  = 32'h50002040 + (ii*4);			
			HTRANS = 2'b10;
			HSIZE  = 3'b010;			//32bit
			#(CYCLE); 
			HSEL_1 = 0;
			HWRITE = 0;
			HADDR  = 32'h0;			
			HTRANS = 2'b0;
			HSIZE = 3'b0;			  	//32bit
			sta_buf= HRDATA;					//Reset SM3
			ii = ii+1;
		end
	   kk = kk + 1;
    end
end
    
endmodule
